Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables
Department of Computer Science
University of Arizona
Tucson, AZ 85721, U.S.A.
EPIC (Explicitly Parallel Instruction Computing) architectures, exemplified by the Intel Itanium, support a number of advanced architectural features designed to get around low-level performance bottlenecks and improve performance. Such features include explicit instruction-level parallelism, instruction predication, and speculative loads from memory. These features are exposed to the compiler, i.e., it is the compiler's responsibility to generate code in a way that can exploit these hardware features. It turns out, however, that compiler optimizations to take advantage of such architectural features can profoundly restructure the program's code, making it potentially difficult to reconstruct the original program logic from an optimized Itanium executable. This paper describes several techniques to undo some of the effects of such optimizations and thereby improve the quality of reverse engineering such executables.