University of Wisconsin
|Topic:||Architectural Support for Synchronization|
|Date:||Thursday, November 15, 2001|
|Place:||Gould-Simpson, Room 701|
The challenge for the computer architect is to turn ever more transistors into better computers. But architectural innovation can sometimes make programming easier as well as improving performance. I will describe some recent developments that improve the performance of parallel applications by exploiting hardware already largely present in modern processors. Surprisingly, these methods reduce the burden on the programmer, making it easier to write correct, efficient parallel programs.